Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control

doi:10.1142/S0218127417500407

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	Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control
	Qiu, Mo 1; Yu, Simin 1; Wen, Yuqiong 1; Lu, Jinhu2 ; He, Jianbin 1; Lin, Zhuosheng 1
	2017-03-01
发表期刊	INTERNATIONAL JOURNAL OF BIFURCATION AND CHAOS
ISSN	0218-1274
卷号	27 期号:3 页码:15
摘要	In this paper, a novel design methodology and its FPGA hardware implementation for a universal chaotic signal generator is proposed via the Verilog HDL fixed-point algorithm and state machine control. According to continuous-time or discrete-time chaotic equations, a Verilog HDL fixed-point algorithm and its corresponding digital system are first designed. In the FPGA hardware platform, each operation step of Verilog HDL fixed-point algorithm is then controlled by a state machine. The generality of this method is that, for any given chaotic equation, it can be decomposed into four basic operation procedures, i.e. nonlinear function calculation, iterative sequence operation, iterative values right shifting and ceiling, and chaotic iterative sequences output, each of which corresponds to only a state via state machine control. Compared with the Verilog HDL floating-point algorithm, the Verilog HDL fixed-point algorithm can save the FPGA hardware resources and improve the operation efficiency. FPGA-based hardware experimental results validate the feasibility and reliability of the proposed approach.
关键词	Chaotic system fixed-point algorithm state machine control Verilog HDL FPGA implementation
DOI	10.1142/S0218127417500407
语种	英语
资助项目	National Key Research and Development Program of China[2016YFB0800401] ; National Natural Science Foundation of China[61532020] ; National Natural Science Foundation of China[61671161] ; National Natural Science Foundation of China[61172023] ; Science and Technology Planning Project of Guangzhou[20151001036]
WOS研究方向	Mathematics ; Science & Technology - Other Topics
WOS类目	Mathematics, Interdisciplinary Applications ; Multidisciplinary Sciences
WOS记录号	WOS:000399165800014
出版者	WORLD SCIENTIFIC PUBL CO PTE LTD
引用统计
文献类型	期刊论文
条目标识符	http://ir.amss.ac.cn/handle/2S8OKBNM/25189
专题	系统科学研究所
通讯作者	Qiu, Mo
作者单位	1.Guangdong Univ Technol, Coll Automat, Guangzhou 510006, Guangdong, Peoples R China 2.Chinese Acad Sci, Acad Math & Syst Sci, Inst Syst Sci, Beijing 100190, Peoples R China
推荐引用方式 GB/T 7714	Qiu, Mo,Yu, Simin,Wen, Yuqiong,et al. Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control[J]. INTERNATIONAL JOURNAL OF BIFURCATION AND CHAOS,2017,27(3):15.
APA	Qiu, Mo,Yu, Simin,Wen, Yuqiong,Lu, Jinhu,He, Jianbin,&Lin, Zhuosheng.(2017).Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control.INTERNATIONAL JOURNAL OF BIFURCATION AND CHAOS,27(3),15.
MLA	Qiu, Mo,et al."Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control".INTERNATIONAL JOURNAL OF BIFURCATION AND CHAOS 27.3(2017):15.