On the optimal four-way switch box routing structures of FPGA greedy routing architectures

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	On the optimal four-way switch box routing structures of FPGA greedy routing architectures
	Pan, JF ; Wu, YL ; Wong, CK ; Yan, GY
	1998-11-01
发表期刊	INTEGRATION-THE VLSI JOURNAL
ISSN	0167-9260
卷号	25 期号:2 页码:137-159
摘要	The problem of mapping a global routing to a detailed routing in a number of 2D routing architectures has been shown to be NP-complete. These routing structures include the Xilinx style routing architecture, as well as architectures with significantly higher switching flexibility. In response to this complexity, a different class of FPGA structures called Greedy Routing Architectures (GRAs), where a locally optimal switch box routing can be greedily extended to an optimal, whole chip routing, was proposed [1-3]. On GRAs, routing of the entire chip can be decomposed into three kinds of four-way switch box routing problems where each can be optimally solved in polynomial time. In this paper, we explore the optimal structures of these four-way switch box routing problems and give the requirement of their minimum routing switches. (C) 1998 Elsevier Science B.V. All rights reserved.
关键词	FPGA routing architecture
语种	英语
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS记录号	WOS:000077630100004
出版者	ELSEVIER SCIENCE BV
引用统计
文献类型	期刊论文
条目标识符	http://ir.amss.ac.cn/handle/2S8OKBNM/13554
专题	应用数学研究所
通讯作者	Wong, CK
作者单位	1.Chinese Univ Hong Kong, Dept Comp Sci & Engn, Hong Kong, Peoples R China 2.Chinese Acad Sci, Inst Appl Math, Beijing 100080, Peoples R China
推荐引用方式 GB/T 7714	Pan, JF,Wu, YL,Wong, CK,et al. On the optimal four-way switch box routing structures of FPGA greedy routing architectures[J]. INTEGRATION-THE VLSI JOURNAL,1998,25(2):137-159.
APA	Pan, JF,Wu, YL,Wong, CK,&Yan, GY.(1998).On the optimal four-way switch box routing structures of FPGA greedy routing architectures.INTEGRATION-THE VLSI JOURNAL,25(2),137-159.
MLA	Pan, JF,et al."On the optimal four-way switch box routing structures of FPGA greedy routing architectures".INTEGRATION-THE VLSI JOURNAL 25.2(1998):137-159.