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On the optimal four-way switch box routing structures of FPGA greedy routing architectures
Pan, JF; Wu, YL; Wong, CK; Yan, GY
1998-11-01
Source PublicationINTEGRATION-THE VLSI JOURNAL
ISSN0167-9260
Volume25Issue:2Pages:137-159
AbstractThe problem of mapping a global routing to a detailed routing in a number of 2D routing architectures has been shown to be NP-complete. These routing structures include the Xilinx style routing architecture, as well as architectures with significantly higher switching flexibility. In response to this complexity, a different class of FPGA structures called Greedy Routing Architectures (GRAs), where a locally optimal switch box routing can be greedily extended to an optimal, whole chip routing, was proposed [1-3]. On GRAs, routing of the entire chip can be decomposed into three kinds of four-way switch box routing problems where each can be optimally solved in polynomial time. In this paper, we explore the optimal structures of these four-way switch box routing problems and give the requirement of their minimum routing switches. (C) 1998 Elsevier Science B.V. All rights reserved.
KeywordFPGA routing architecture
Language英语
WOS Research AreaComputer Science ; Engineering
WOS SubjectComputer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS IDWOS:000077630100004
PublisherELSEVIER SCIENCE BV
Citation statistics
Cited Times:11[WOS]   [WOS Record]     [Related Records in WOS]
Document Type期刊论文
Identifierhttp://ir.amss.ac.cn/handle/2S8OKBNM/13554
Collection中国科学院数学与系统科学研究院
Affiliation1.Chinese Univ Hong Kong, Dept Comp Sci & Engn, Hong Kong, Peoples R China
2.Chinese Acad Sci, Inst Appl Math, Beijing 100080, Peoples R China
Recommended Citation
GB/T 7714
Pan, JF,Wu, YL,Wong, CK,et al. On the optimal four-way switch box routing structures of FPGA greedy routing architectures[J]. INTEGRATION-THE VLSI JOURNAL,1998,25(2):137-159.
APA Pan, JF,Wu, YL,Wong, CK,&Yan, GY.(1998).On the optimal four-way switch box routing structures of FPGA greedy routing architectures.INTEGRATION-THE VLSI JOURNAL,25(2),137-159.
MLA Pan, JF,et al."On the optimal four-way switch box routing structures of FPGA greedy routing architectures".INTEGRATION-THE VLSI JOURNAL 25.2(1998):137-159.
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